Due to the shrinking size and the fast increasing density of the components in semiconductor devices, conduction within a single layer can't fulfil the demands in the nano semiconductor process anymore. Multi-layer conduction is therefore developed. With increasing resolution, the depth of focus in patterning process is reduced, so advanced planarization technique is required. Currently, chemical mechanical planarization (CMP) is the key technique for global planarization.
On the other hand, low dielectric insulating layer is widely used to improve the conduction between components. The RC delay time can be reduced, for example, by adding organic compounds to the traditional insulating layers such as: silica, boron phosphosilicate glass, phosphosilicate glass, borosilicate glass, and florine-added silica.
Traditional silica-based slurry for CMP has low polish rate and is easy to cause scratches on the wafers. Yoshio H., Taeshi F. etc. at Hitachi chemistry use cerium oxide-based slurry instead. The polish rate cerium-based slurry on SOG and thermal oxide is at least five times higher than commercial silica-based slurry CABOT SC-1. They also found that adding organic compounds to silica can not only result in low dielectric constant but also reduce the polish rate of CMP.
So far, no adequate slurry for CMP of organic SOG insulating layer, which can provide satisfying polish rate, is available.